SystemVerilog Verification Methodology – using VMM (Pre-UVM)

Basic verification methodology course intended for engineers familiar with SystemVerilog language. This course uses VMM base class library as vehicle, but the concepts are equally applicable in all other libraries such as OVM, UVM. AVM, eRM etc. We start from the basics, introduce the top-level architecture of testbench, then delve into each of the components. For those looking for UVM equivalents, below correlation may help:

1. Section 1-3: Common across BCLs (Base Class Libraries)

2. Section 4: Transaction Modeling – UVM transactions/sequence items

3. Section 5: TLM Ports/Channels – UVM SEQ Item port/analysis ports

4. Section 6: Constrained Random Generation – UVM Sequences, SEQ macros

5. Section 7: Driver BFM – UVM Driver, Monitor BFM

6. Section 8: Complete Env – UVM ENV

7. Section 9: Controlling the test flow – UVM Phasing

Intention of each short section is to let the learners digest each piece in short and understand the rationale behind methodology guidelines. Goal is NOT to teach the syntax, rather explore why such guidelines are important, what are the common mistakes engineers do without these methodologies etc. If you need a full-fledged course on UVM with syntax, labs etc. feel free to contact us via [email protected] for a paid course.

This material is from an earlier recording at a training session and has some background hiss/noise, bear with us while we attempt to fix the same.